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Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…
By Srinivas Velivala Design rule checking (DRC) closure is a “tax” that custom layout designers must pay at all process nodes. Ask all...
Oct 11, 20213 min read

日月光與西門子協同合作下一代高密度先進封裝設計驗證解決方案
日月光與西門子數字工業軟體公司協同合作新的設計驗證解決方案,協助共同客戶更易於建立和評估多樣複雜的IC封裝技術與高密度連結的設計,且能在執行實體設計之前和設計期間使用更具相容性與穩定性的實體設計驗證環境。 高密度先進封裝解決方案(HDAP)源自于日月光參與西門子半導體封裝聯...
Sep 29, 20212 min read


Making sense of cloud EDA
By Michael White and Omar El-Sewefy How to carry out a sensible analysis of cloud EDA’s potential, so you get the right tools and...
Sep 27, 20218 min read


Caution! Avoid detours when improving resistance on ESD paths
By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused by...
Sep 22, 20212 min read


Get rid of GUI frustration and speed up your Calibre verification job submissions!
By Slava Zhuchenya Graphical user interface (GUI) frustration is real. Deployment of integrated circuit (IC) physical and circuit...
Sep 16, 20212 min read


So you think you know symmetry? Think again…
By Sherif Hany “The Art of Analog Layout” is one of the canonical books addressing concepts behind layout design techniques used in...
Sep 6, 20212 min read


Can we just agree that perception is everything? Especially in IC design?
By Dennis Joseph Is the dress black and blue, or white and gold? Is that a rabbit or a duck? People looking at the exact same image often...
Aug 19, 20213 min read

西門子EDA如何破解先進制程最新挑戰
隨著AI時代的到來,市場上對大資料處理速度的需求越來越高。眾所周知,工藝制程的進步是實現高性能計算最為有效的途徑之一。因此,市場對先進制程的需求也會越來越旺盛。根據IC Insights發佈的《2020-2024年全球晶圓產能》報告顯示,從2024年開始,先進工藝的IC產能...
Jul 26, 20214 min read


Efficient package delivery is not just for FedEx!
By John Ferguson Cost, risk, and the limitations of monolithic scaling are driving growth in multi-die (heterogeneous) advanced IC...
Jul 15, 20211 min read
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