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May 17, 20222 min read
The “next” technology node: ready or not, here it comes
By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named by its...
May 3, 20224 min read
TOREX uses Siemens EDA tools to satisfy IC requirements and shorten design cycles
Using Tanner design tools, TOREX has developed the smallest converters possible without sacrificing functionality and performance....
Apr 26, 202211 min read
Tanner 應用系列｜適合類比 / 混合訊號 IC 設計的全流程解決方案
Siemens EDA IC 全流程 Siemens EDA 全流程有一個豐富的環境，高度可配置且非常靈活，為混合信號設計人員提供了許多易用功能。該流程經過優化，適用於創建 22nm 的定制模擬 IC 或 “類比為頂層” 的混合訊號...
Apr 11, 20223 min read
What’s New in Tanner Tools v2021.2?
Improved Handling of Array Creation and Spacing in L-Edit Using Alignment Operations Tile2DArray icon now controls rows/columns when all...
Apr 5, 20222 min read
Learn the secret to generating signoff fill in P&R and accelerating your tapeouts
By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows to ensure designs...
Mar 29, 20224 min read
A Powerful Analog Verification Platform for Samsung Foundry’s Advanced Technologies
By Pradeep Thiagarajan Having done IC development for over two decades, I can appreciate the complexities of foundry processes that...
Mar 8, 20227 min read
Taking 2.5D/3DIC physical verification to the next level
Introduction The adoption of high-density advanced packaging (HDAP) continues to grow for all kinds of end-user applications. 2.5D...
Jan 25, 20221 min read
MaxLinear and Calibre RealTime Digital: Signoff DRC in P&R
Place and route (P&R) engineers at MaxLinear strive to achieve high reliability and manufacturability in their SoC designs, while also...
Jan 24, 20222 min read
Siemens collaborates with UMC on design kits for automotive and power applications
Siemens has collaborated with United Microelectronics Corporation (UMC) to develop process design kits (PDKs) for the foundry‘s...
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